Eliyan Corporation has announced the successful delivery of first silicon for its NuLink-2.0 PHY, manufactured in a 3nm process, achieving 64Gbps per bump performance that sets a new industry standard for die-to-die PHY solutions. This breakthrough in chiplet interconnect technology represents a major leap forward in multi-die architecture capabilities, effectively doubling the bandwidth of die-to-die connectivity while maintaining compatibility with the UCIe standard. The technology delivers unprecedented improvements in power efficiency, area utilization, and latency across both standard and advanced packaging.
The implications of this development are substantial for high-performance computing applications, particularly in artificial intelligence, high-performance computing, and gaming sectors. The NuLink-2.0 PHY's ability to support both standard and advanced packaging offers enhanced flexibility to manufacturers, while its UMI technology improves Die-to-Memory bandwidth by more than twofold. This advancement addresses critical challenges in scaling semiconductor performance, size, power consumption, and cost as demand for more powerful computing solutions grows across industries.
One of the key advantages of the NuLink-2.0 PHY is its cost-effectiveness and scalability, enabling high-performance multi-die architectures at lower power and reduced costs. This makes the solution applicable to a wide range of markets beyond traditional computing, including aerospace, automotive, and industrial applications that stand to benefit from this technology. The emphasis on increased sustainability through reduction in costs, manufacturing waste, and power consumption aligns with growing industry concerns about environmental impact, as detailed in industry discussions about semiconductor sustainability at https://www.semiconductors.org/sustainability.
The successful delivery in a 3nm process node demonstrates the ability to push semiconductor manufacturing boundaries at advanced nodes, showcasing Eliyan's technical capabilities while pointing to potential for continued innovation in chiplet-based designs. As the industry moves toward more complex multi-die architectures to meet next-generation computing demands, efficient and high-performance chiplet interconnects become crucial. Eliyan's breakthrough could pave the way for new design possibilities, enabling system architects to create more powerful and efficient computing solutions across various applications.
Beyond immediate performance gains, this technology could contribute to reducing the overall carbon footprint of high-performance computing systems by enabling more efficient multi-die architectures. This aligns with broader industry efforts to improve energy efficiency and sustainability in data centers and other computing-intensive environments, as explored in research on data center energy efficiency at https://www.iea.org/reports/data-centres-and-data-transmission-networks. The delivery of the industry's highest performing chiplet interconnect PHY at 64Gbps in a 3nm process marks a significant milestone that will play a crucial role in shaping future computing architectures and enabling next-generation high-performance, sustainable computing solutions.
